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| INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: * The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications * The IC06 74HC/HCT/HCU/HCMOS Logic Package Information * The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT139 Dual 2-to-4 line decoder/demultiplexer Product specification File under Integrated Circuits, IC06 September 1993 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer FEATURES * Demultiplexing capability * Two independent 2-to-4 decoders * Multifunction capability * Active LOW mutually exclusive outputs * Output capability: standard * ICC category: MSI GENERAL DESCRIPTION 74HC/HCT139 The 74HC/HCT139 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard no. 7A. The 74HC/HCT139 are high-speed, dual 2-to-4 line decoder/multiplexers. This device has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable can be used as the data input for a 1-to-4 demultiplexer application. The "139" is identical to the HEF4556 of the HE4000B family. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf = 6 ns TYPICAL SYMBOL tPHL/ tPLH PARAMETER propagation delay nAn to nYn nE3 to nYn CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W): PD = CPD x VCC2 x fi + (CL x VCC2 x fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL x VCC2 x fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V APPLICATIONS * Memory decoding or data-routing * Code conversion ORDERING INFORMATION See "74HC/HCT/HCU/HCMOS Logic Package Information". September 1993 2 input capacitance power dissipation capacitance per multiplexer notes 1 and 2 CONDITIONS HC CL = 15 pF; VCC = 5 V 11 10 3.5 42 13 13 3.5 44 ns ns pF pF HCT UNIT Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer PIN DESCRIPTION PIN NO. 1, 15 2, 3 4, 5, 6, 7 8 12, 11, 10, 9 14, 13 16 SYMBOL 1E, 2E 1A0, 1A1 1Y0 to 1Y3 GND 2Y0 to 2Y3 2A0, 2A1 VCC NAME AND FUNCTION enable inputs (active LOW) address inputs outputs (active LOW) ground (0 V) outputs (active LOW) address inputs positive supply voltage 74HC/HCT139 Fig.1 Pin configuration. Fig.2 Logic symbol. (a) (b) Fig.3 IEC logic symbol. September 1993 3 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer 74HC/HCT139 Fig.4 Functional diagram. FUNCTION TABLE INPUTS nE H L L L L Notes 1. H = HIGH voltage level L = LOW voltage level X = don't care nA0 X L H L H nA1 X L L H H nY0 H L H H H OUTPUTS nY1 H H L H H nY2 H H H L H nY3 H H H H L Fig.5 Logic diagram (one decoder/demultiplexer). September 1993 4 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer DC CHARACTERISTICS FOR 74HC For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI AC CHARACTERISTICS FOR 74HC GND = 0 V; tr = tf = 6 ns; CL = 50 pF Tamb (C) 74HC SYMBOL PARAMETER min. tPHL/ tPLH propagation delay nAn to Yn propagation delay nE to nYn output transition time +25 typ. 39 14 11 33 12 10 19 7 6 max. 145 29 25 135 27 23 75 15 13 -40 to +85 min. max. 180 36 31 170 34 29 95 19 16 -40 to +125 min. max. 220 44 38 205 41 35 110 22 19 ns UNIT 74HC/HCT139 TEST CONDITIONS VCC WAVEFORMS (V) 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 Fig.6 tPHL/ tPLH ns Fig.7 tTHL/ tTLH ns Figs 6 and 7 September 1993 5 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer DC CHARACTERISTICS FOR HCT For the DC characteristics see "74HC/HCT/HCU/HCMOS Logic Family Specifications". Output capability: standard ICC category: MSI Note to HCT types 74HC/HCT139 The value of additional quiescent supply current (ICC) for a unit load of 1 is given in the family specifications. To determine ICC per input, multiply this value by the unit load coefficient shown in the table below. INPUT 1An 2An nE UNIT LOAD 0.70 0.70 1.35 COEFFICIENT AC CHARACTERISTICS FOR 74HCT GND = 0 V; tf = tf = 6 ns; CL = 50 pF Tamb (C) 74HCT SYMBOL PARAMETER min. tPHL/ tPLH tPHL/ tPLH tTHL/ tTLH propagation delay nAn to Yn propagation delay nE to nYn output transition time +25 typ. 16 16 7 max. 34 34 15 -40 to +85 min. max. 43 43 19 -40 to +125 min. max. 51 51 22 ns ns ns 4.5 4.5 4.5 Fig.6 Fig.7 Figs 6 and 7 UNIT VCC WAVEFORMS (V) TEST CONDITIONS September 1993 6 Philips Semiconductors Product specification Dual 2-to-4 line decoder/demultiplexer AC WAVEFORMS 74HC/HCT139 (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.6 Waveforms showing the address input (nAn) to output (nYn) propagation delays and the output transition times. (1) HC : VM = 50%; VI = GND to VCC. HCT: VM = 1.3 V; VI = GND to 3 V. Fig.7 Waveforms showing the enable input (nE) to output (nYn) propagation delays and the output transition times. PACKAGE OUTLINES See "74HC/HCT/HCU/HCMOS Logic Package Outlines". September 1993 7 |
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